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DDR SDRAM

Part No. W9412G6JH
Datasheet  W9412G6JH.pdf
Description The W9412G6JH is a 128M DDR SDRAM and speed involving -4/-5/-5I/-5K/-6/-6I
Status: Mass Production
Features
  • 2.5V ±0.2V Power Supply for DDR400/333
  • 2.4V~2.7V Power Supply for DDR500
  • Up to 250 MHz Clock Frequency
  • Double Data Rate architecture; two data transfers per clock cycle
  • Differential clock inputs (CLK and /CLK)
  • DQS is edge-aligned with data for Read; center-aligned with data for Write
  • CAS Latency: 2, 2.5, 3 and 4
  • Burst Length: 2, 4 and 8
  • Auto Refresh and Self Refresh
  • Precharged Power Down and Active Power Down
  • Write Data Mask
  • Write Latency = 1
  • 15.6 μS refresh interval (4K/64 mS Refresh), @ -40°C ≦ TA ≦ 85°C
  • 3.9 μS refresh interval (4K/16 mS Refresh), @ 85°C < TA ≦ 105°C
  • Maximum burst refresh cycle: 8
  • Interface: SSTL_2

* Not support self refresh function with TA > 85°C

Diagram N/A
Package Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
Other Files IBIS Model W9412G6JH_ibs.zip 
Spice Model N/A 
Verilog Model W9412G6JH_verilog.zip
Development Tools N/A
Others N/A

Contact us: SDRAM@winbond.com